it's part of an 8086 PC emulator, where it checks what opcode is about to be run, and then takes appropriate action. according to the wiki, FB is "not yet an optimizing compiler" so if that's the case, then this should drastically speed up my code since it wouldn't be turning the select case into a jump table.
here is the original select case block: (Sorry some of the indentation looks messed up, i accidentally used spaces in some part instead of tabs so it looks goofy when pasted here. it looks good in FbEdit)
Code: Select all
Select Case opcode
Case &H0 '00 ADD Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b + oper2b
flag_add8 oper1b, oper2b
writerm8(rm, res8)
Case &H1 '01 ADD Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 + oper2
flag_add16 oper1, oper2
writerm16(rm, res16)
Case &H2 '02 ADD Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b + oper2b
flag_add8 oper1b, oper2b
putreg8(reg, res8)
Case &H3 '03 ADD Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 + oper2
flag_add16 oper1, oper2
putreg16(reg, res16)
Case &H4 '04 ADD regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b + oper2b
flag_add8 oper1b, oper2b
regal = res8
Case &H5 '05 ADD eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 + oper2
flag_add16 oper1, oper2
regah = res16 Shr 8: regal = res16 And 255
Case &H6 '06 PUSH reges
push reges
Case &H7 '07 POP reges
reges = pop
Case &H8 '08 OR Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b Or oper2b
flag_log8(res8)
writerm8(rm, res8)
Case &H9 '09 OR Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 Or oper2
flag_log16(res16)
writerm16(rm, res16)
Case &HA '0A OR Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b Or oper2b
flag_log8(res8)
putreg8(reg, res8)
Case &HB '0B OR Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 Or oper2
flag_log16(res16)
putreg16(reg, res16)
Case &HC '0C OR regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b Or oper2b
flag_log8(res8)
regal = res8
Case &HD '0D OR eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 Or oper2
flag_log16(res16)
regah = res16 Shr 8: regal = res16 And 255
Case &HE '0E PUSH regcs
push regcs
Case &H10 '10 ADC Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b + oper2b + cf
flag_adc8 oper1b, oper2b, cf
writerm8(rm, res8)
Case &H11 '11 ADC Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 + oper2 + cf
flag_adc16 oper1, oper2, cf
writerm16(rm, res16)
Case &H12 '12 ADC Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b + oper2b + cf
flag_adc8 oper1b, oper2b, cf
putreg8(reg, res8)
Case &H13 '13 ADC Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 + oper2 + cf
flag_adc16 oper1, oper2, cf
putreg16(reg, res16)
Case &H14 '14 ADC regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b + oper2b + cf
flag_adc8 oper1b, oper2b, cf
regal = res8
Case &H15 '15 ADC eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 + oper2 + cf
flag_adc16 oper1, oper2, cf
regah = res16 Shr 8: regal = res16 And 255
Case &H16 '16 PUSH regss
push regss
Case &H17 '17 POP regss
regss = pop
Case &H18 '18 SBB Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b - (oper2b + cf)
flag_sbb8 oper1b, oper2b, cf
writerm8(rm, res8)
Case &H19 '19 SBB Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 - (oper2 + cf)
flag_sbb16 oper1, oper2, cf
writerm16(rm, res16)
Case &H1A '1A SBB Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b - (oper2b + cf)
flag_sbb8 oper1b, oper2b, cf
putreg8(reg, res8)
Case &H1B '1B SBB Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 - (oper2 + cf)
flag_sbb16 oper1, oper2, cf
putreg16(reg, res16)
Case &H1C '1C SBB regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b - (oper2b + cf)
flag_sbb8 oper1b, oper2b, cf
regal = res8
Case &H1D '1D SBB eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 - (oper2 + cf)
flag_sbb16 oper1, oper2, cf
regah = res16 Shr 8: regal = res16 And 255
Case &H1E '1E PUSH regds
push regds
Case &H1F '1F POP regds
regds = pop
Case &H20 '20 AND Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b And oper2b
flag_log8(res8)
writerm8(rm, res8)
Case &H21 '21 AND Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 And oper2
flag_log16(res16)
writerm16(rm, res16)
Case &H22 '22 AND Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b And oper2b
flag_log8(res8)
putreg8(reg, res8)
Case &H23 '23 AND Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 And oper2
flag_log16(res16)
putreg16(reg, res16)
Case &H24 '24 AND regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b And oper2b
flag_log8(res8)
regal = res8
Case &H25 '25 AND eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 And oper2
flag_log16(res16)
regah = res16 Shr 8: regal = res16 And 255
Case &H27 '27 DAA
If ((regal And &HF&) > 9) Or (af = 1) Then
oper1 = regal + 6
regal = oper1 And 255
If (oper1 And &HFF00&) Then cf = 1 Else cf = 0
af = 1
Else
af = 0
End If
If ((regal And &HF0&) > &H90&) Or (cf = 1) Then
regal = regal + &H60&
cf = 1
Else
cf = 0
End If
regal = regal And 255
flag_szp8(regal)
Case &H28 '28 SUB Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b - oper2b
flag_sub8 oper1b, oper2b
writerm8(rm, res8)
Case &H29 '29 SUB Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 - oper2
flag_sub16 oper1, oper2
writerm16(rm, res16)
Case &H2A '2A SUB Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b - oper2b
flag_sub8 oper1b, oper2b
putreg8(reg, res8)
Case &H2B '2B SUB Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 - oper2
flag_sub16 oper1, oper2
putreg16(reg, res16)
Case &H2C '2C SUB regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b - oper2b
flag_sub8 oper1b, oper2b
regal = res8
Case &H2D '2D SUB eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 - oper2
flag_sub16 oper1, oper2
regah = res16 Shr 8: regal = res16 And 255
Case &H2F '2F DAS
If ((regal And 15) > 9) Or (af = 1) Then
oper1 = regal - 6
regal = oper1 And 255
If (oper1 And &HFF00&) Then cf = 1 Else cf = 0
af = 1
Else
af = 0
End If
If ((regal And &HF0) > &H90&) Or (cf = 1) Then
regal = regal - &H60&
cf = 1
Else
cf = 0
End If
flag_szp8(regal)
Case &H30 '30 XOR Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
res8 = oper1b Xor oper2b
flag_log8(res8)
writerm8(rm, res8)
Case &H31 '31 XOR Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
res16 = oper1 Xor oper2
flag_log16(res16)
writerm16(rm, res16)
Case &H32 '32 XOR Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
res8 = oper1b Xor oper2b
flag_log8(res8)
putreg8(reg, res8)
Case &H33 '33 XOR Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
res16 = oper1 Xor oper2
flag_log16(res16)
putreg16(reg, res16)
Case &H34 '34 XOR regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
res8 = oper1b Xor oper2b
flag_log8(res8)
regal = res8
Case &H35 '35 XOR eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
res16 = oper1 Xor oper2
flag_log16(res16)
regah = res16 Shr 8: regal = res16 And 255
Case &H37 '37 AAA ASCII
If ((regal And &HF&) > 9) Or (af = 1) Then
regal = regal + 6
regah = regah + 1
af = 1
cf = 1
Else
af = 0
cf = 0
End If
regal = regal And &HF&
Case &H38 '38 CMP Eb Gb
modregrm()
oper1b = readrm8(rm): oper2b = getreg8(reg)
flag_sub8 oper1b, oper2b
If debugmode = 1 Then dprint " CMP 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
Case &H39 '39 CMP Ev Gv
modregrm()
oper1 = readrm16(rm): oper2 = getreg16(reg)
flag_sub16 oper1, oper2
If debugmode = 1 Then dprint " CMP 16-bit: oper1 = " + Hex$(oper1) + "h, oper2 = " + Hex$(oper2) + "h"
Case &H3A '3A CMP Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
flag_sub8 oper1b, oper2b
If debugmode = 1 Then dprint " CMP 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
Case &H3B '3B CMP Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
flag_sub16 oper1, oper2
If debugmode = 1 Then dprint " CMP 16-bit: oper1 = " + Hex$(oper1) + "h, oper2 = " + Hex$(oper2) + "h"
Case &H3C '3C CMP regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
flag_sub8 oper1b, oper2b
If debugmode = 1 Then dprint " CMP 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
Case &H3D '3D CMP eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
flag_sub16 oper1, oper2
If debugmode = 1 Then dprint " CMP 16-bit: oper1 = " + Hex$(oper1) + "h, oper2 = " + Hex$(oper2) + "h"
Case &H3F '3F AAS ASCII
If ((regal And &HF&) > 9) Or (af = 1) Then
regal = regal - 6
regah = regah - 1
af = 1
cf = 1
Else
af = 0
cf = 0
End If
regal = regal And &HF&
Case &H40 '40 INC eAX
oldcf = cf
oper1 = ((regah Shl 8) Or regal): oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
regah = res16 Shr 8: regal = res16 And 255
Case &H41 '41 INC eCX
oldcf = cf
oper1 = ((regch Shl 8) Or regcl): oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
putreg16(regcx, res16)
Case &H42 '42 INC eDX
oldcf = cf
oper1 = ((regdh Shl 8) Or regdl): oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
putreg16(regdx, res16)
Case &H43 '43 INC eBX
oldcf = cf
oper1 = ((regbh Shl 8) Or regbl): oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
putreg16(regbx, res16)
Case &H44 '44 INC eSP
oldcf = cf
oper1 = regsp: oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
regsp = res16
Case &H45 '45 INC eBP
oldcf = cf
oper1 = regbp: oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
regbp = res16
Case &H46 '46 INC eSI
oldcf = cf
oper1 = regsi: oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
regsi = res16
Case &H47 '47 INC eDI
oldcf = cf
oper1 = regdi: oper2 = 1
res16 = oper1 + oper2
flag_add16 oper1, oper2
cf = oldcf
regdi = res16
Case &H48 '48 DEC eAX
oldcf = cf
oper1 = ((regah Shl 8) Or regal): oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
regah = res16 Shr 8: regal = res16 And 255
Case &H49 '49 DEC eCX
oldcf = cf
oper1 = ((regch Shl 8) Or regcl): oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
putreg16(regcx, res16)
Case &H4A '4A DEC eDX
oldcf = cf
oper1 = ((regdh Shl 8) Or regdl): oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
putreg16(regdx, res16)
Case &H4B '4B DEC eBX
oldcf = cf
oper1 = ((regbh Shl 8) Or regbl): oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
putreg16(regbx, res16)
Case &H4C '4C DEC eSP
oldcf = cf
oper1 = regsp: oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
regsp = res16
Case &H4D '4D DEC eBP
oldcf = cf
oper1 = regbp: oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
regbp = res16
Case &H4E '4E DEC eSI
oldcf = cf
oper1 = regsi: oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
regsi = res16
Case &H4F '4F DEC eDI
oldcf = cf
oper1 = regdi: oper2 = 1
res16 = oper1 - oper2
flag_sub16 oper1, oper2
cf = oldcf
regdi = res16
Case &H50 '50 PUSH eAX
push ((regah Shl 8) Or regal)
Case &H51 '51 PUSH eCX
push ((regch Shl 8) Or regcl)
Case &H52 '52 PUSH eDX
push ((regdh Shl 8) Or regdl)
Case &H53 '53 PUSH eBX
push ((regbh Shl 8) Or regbl)
Case &H54 '54 PUSH eSP
push regsp
Case &H55 '55 PUSH eBP
push regbp
Case &H56 '56 PUSH eSI
push regsi
Case &H57 '57 PUSH eDI
push regdi
Case &H58 '58 POP eAX
res16 = pop
regah = res16 Shr 8: regal = res16 And 255
Case &H59 '59 POP eCX
res16 = pop
regch = res16 Shr 8: regcl = res16 And 255
Case &H5A '5A POP eDX
res16 = pop
regdh = res16 Shr 8: regdl = res16 And 255
Case &H5B '5B POP eBX
res16 = pop
regbh = res16 Shr 8: regbl = res16 And 255
Case &H5C '5C POP eSP
regsp = getmem16(regss, regsp)
Case &H5D '5D POP eBP
regbp = pop
Case &H5E '5E POP eSI
regsi = pop
Case &H5F '5F POP eDI
regdi = pop
Case &H60 '60 PUSHA (80186+)
oldsp = regsp
push ((regah Shl 8) Or regal)
push ((regch Shl 8) Or regcl)
push ((regdh Shl 8) Or regdl)
push ((regbh Shl 8) Or regbl)
push oldsp: push regbp: push regsi: push regdi
Case &H61 '61 POPA (80186+)
regdi = pop: regsi = pop: regbp = pop: dummy = pop
putreg16(regbx, pop): putreg16(regdx, pop): putreg16(regcx, pop): putreg16(regax, pop)
Case &H68 '68 PUSH Iv (80186+)
push getmem16(regcs, ip): StepIP 2
Case &h69 '69 IMUL Ev Iv (80186+)
modregrm()
temp1 = readrm16(rm)
temp2 = getmem16(regcs, ip): StepIP 2
If (temp1 And &H8000&) = &H8000& Then temp1 = temp1 Or &HFFFF0000
If (temp2 And &H8000&) = &H8000& Then temp2 = temp2 Or &HFFFF0000
temp3 = (temp1 * temp2) And &HFFFFFFFF
putreg16(regax, temp3 And &HFFFF&)
putreg16(regdx, temp3 Shr 16)
If ((regdh Shl 8) Or regdl) <> 0 Then cf = 1: of = 1 Else cf = 0: of = 0
Case &h6A '6A PUSH Ib (80186+)
push getmem8(regcs, ip): StepIP 1
Case &h6B '6B IMUL Eb Ib (80186+)
modregrm()
oper1 = signext(readrm8(rm))
temp1 = signext(getmem8(regcs, ip)): StepIP 1
temp2 = oper1
If (temp1 And &H80&) = &H80& Then temp1 = temp1 Or &HFFFFFF00
If (temp2 And &H80&) = &H80& Then temp2 = temp2 Or &HFFFFFF00
temp3 = (temp1 * temp2) And &HFFFF&
putreg16(regax, temp3)
If regah <> 0 Then cf = 1: of = 1 Else cf = 0: of = 0
Case &h6C To &h6F '80186 port operations, just act as if they're NOPs for now...
StepIP(1) 'they have a modregrm() byte we must skip...
Case &H70 '70 JO Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If of <> 0 Then ip = ip + temp16
Case &H71 '71 JNO Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If of = 0 Then ip = ip + temp16
Case &H72 '72 JB Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If cf <> 0 Then ip = ip + temp16
Case &H73 '73 JNB Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If cf = 0 Then ip = ip + temp16
Case &H74 '74 JZ Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If zf <> 0 Then ip = ip + temp16
Case &H75 '75 JNZ Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If zf = 0 Then ip = ip + temp16
Case &H76 '76 JBE Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (cf <> 0) Or (zf <> 0) Then ip = ip + temp16
Case &H77 '77 JA Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (cf = 0) And (zf = 0) Then ip = ip + temp16
Case &H78 '78 JS Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If sf <> 0 Then ip = ip + temp16
Case &H79 '79 JNS Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If sf = 0 Then ip = ip + temp16
Case &H7A '7A JPE Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If pf <> 0 Then ip = ip + temp16
Case &H7B '7B JPO Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If pf = 0 Then ip = ip + temp16
Case &H7C '7C JL Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (sf <> of) Then ip = ip + temp16
Case &H7D '7D JGE Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (sf = of) Then ip = ip + temp16
Case &H7E '7E JLE Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (sf <> of) Or (zf <> 0) Then ip = ip + temp16
Case &H7F '7F JG Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If (zf = 0) And (sf = of) Then ip = ip + temp16
Case &H80, &H82 '80/82 GRP1 Eb Ib
modregrm()
oper1b = readrm8(rm): oper2b = getmem8(regcs, ip): StepIP 1
op_grp1(0)
If reg < 7 Then
writerm8(rm, res8)
End If
Case &H81 '81 GRP1 Ev Iv
modregrm()
oper1 = readrm16(rm): oper2 = getmem16(regcs, ip): StepIP 2
op_grp1(1)
If reg < 7 Then
writerm16(rm, res16)
End If
Case &H83 '83 GRP1 Ev Ib
modregrm()
oper1 = readrm16(rm): oper2 = signext(getmem8(regcs, ip)): StepIP 1
op_grp1(1)
If reg < 7 Then
writerm16(rm, res16)
End If
Case &H84 '84 TEST Gb Eb
modregrm()
oper1b = getreg8(reg): oper2b = readrm8(rm)
flag_log8(oper1b And oper2b)
If debugmode = 1 Then dprint " TEST 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
Case &H85 '85 TEST Gv Ev
modregrm()
oper1 = getreg16(reg): oper2 = readrm16(rm)
flag_log16(oper1 And oper2)
Case &H86 '86 XCHG Gb Eb
modregrm()
oper1b = getreg8(reg)
putreg8(reg, readrm8(rm))
writerm8(rm, oper1b)
Case &H87 '87 XCHG Gv Ev
modregrm()
oper1 = getreg16(reg)
putreg16(reg, readrm16(rm))
writerm16(rm, oper1)
Case &H88 '88 MOV Eb Gb
modregrm()
writerm8(rm, getreg8(reg))
Case &H89 '89 MOV Ev Gv
modregrm()
writerm16(rm, getreg16(reg))
Case &H8A '8A MOV Gb Eb
modregrm()
putreg8(reg, readrm8(rm))
Case &H8B '8B MOV Gv Ev
modregrm()
putreg16(reg, readrm16(rm))
Case &H8C '8C MOV Ew Sw
modregrm()
writerm16(rm, getsegreg(reg))
Case &H8D '8D LEA Gv M
modregrm()
getea(rm)
putreg16(reg, ea - useseg * 16)
Case &H8E '8E MOV Sw Ew
modregrm()
putsegreg(reg, readrm16(rm))
Case &H8F '8F POP Ev
modregrm()
writerm16(rm, pop)
Case &H90 '90 NOP
Case &H91 '91 XCHG eCX eAX
oper1b = regch
oper2b = regcl
regch = regah
regcl = regal
regah = oper1b
regal = oper2b
Case &H92 '92 XCHG eDX eAX
oper1b = regdh
oper2b = regdl
regdh = regah
regdl = regal
regah = oper1b
regal = oper2b
Case &H93 '93 XCHG eBX eAX
oper1b = regbh
oper2b = regbl
regbh = regah
regbl = regal
regah = oper1b
regal = oper2b
Case &H94 '94 XCHG eSP eAX
oper1 = regsp
regsp = ((regah Shl 8) Or regal)
regah = oper1 Shr 8: regal = oper1 And 255
Case &H95 '95 XCHG eBP eAX
oper1 = regbp
regbp = ((regah Shl 8) Or regal)
regah = oper1 Shr 8: regal = oper1 And 255
Case &H96 '96 XCHG eSI eAX
oper1 = regsi
regsi = ((regah Shl 8) Or regal)
regah = oper1 Shr 8: regal = oper1 And 255
Case &H97 '97 XCHG eDI eAX
oper1 = regdi
regdi = ((regah Shl 8) Or regal)
regah = oper1 Shr 8: regal = oper1 And 255
Case &H98 '98 CBW
If (regal And &h80) = &h80 Then regah = &hFF Else regah = 0
Case &H99 '99 CWD
If (regah And &h80) = &h80 Then
putreg16(regdx, &hFFFF)
Else
putreg16(regdx, 0)
End If
Case &h9A '9A CALL Ap
oper1 = getmem16(regcs, ip): StepIP 2
oper2 = getmem16(regcs, ip): StepIP 2
push regcs: push ip: ip = oper1: regcs = oper2
Case &H9B '9B WAIT
Case &H9C '9C PUSHF
push makeflagsword And &hFFF
Case &H9D '9D POPF
decodeflagsword pop
Case &H9E '9E SAHF
decodeflagsword (makeflagsword And &HFF00&) + regah
Case &H9F '9F LAHF
regah = makeflagsword And &hFF
Case &HA0 'A0 MOV regal Ob
regal = getmem8(useseg, getmem16(regcs, ip)): StepIP 2
Case &HA1 'A1 MOV eAX Ov
oper1 = getmem16(useseg, getmem16(regcs, ip)): StepIP 2
regah = oper1 Shr 8: regal = oper1 And 255
Case &HA2 'A2 MOV Ob regal
putmem8 useseg, getmem16(regcs, ip), regal: StepIP 2
Case &HA3 'A3 MOV Ov eAX
putmem16 useseg, getmem16(regcs, ip), ((regah Shl 8) Or regal): StepIP 2
Case &HA4 'A4 MOVSB
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
putmem8 reges, regdi, getmem8(useseg, regsi)
If df Then regsi = regsi - 1: regdi = regdi - 1 Else regsi = regsi + 1: regdi = regdi + 1
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HA5 'A5 MOVSW
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
putmem16 reges, regdi, getmem16(useseg, regsi)
If df Then regsi = regsi - 2: regdi = regdi - 2 Else regsi = regsi + 2: regdi = regdi + 2
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HA6 'A6 CMPSB
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
oper1b = getmem8(useseg, regsi): oper2b = getmem8(reges, regdi)
If df Then regsi = regsi - 1: regdi = regdi - 1 Else regsi = regsi + 1: regdi = regdi + 1
flag_sub8 oper1b, oper2b
If debugmode = 1 Then dprint " CMP 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
If (reptype = 1) And (zf = 0) Then Exit Do
If (reptype = 2) And (zf = 1) Then Exit Do
Loop Until reptype = 0
Case &HA7 'A7 CMPSW
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
oper1 = getmem16(useseg, regsi): oper2 = getmem16(reges, regdi)
If df Then regsi = regsi - 2: regdi = regdi - 2 Else regsi = regsi + 2: regdi = regdi + 2
flag_sub16 oper1, oper2
If debugmode = 1 Then dprint " CMP 16-bit: oper1 = " + Hex$(oper1) + "h, oper2 = " + Hex$(oper2) + "h"
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
If (reptype = 1) And (zf = 0) Then Exit Do
If (reptype = 2) And (zf = 1) Then Exit Do
Loop Until reptype = 0
Case &HA8 'A8 TEST regal Ib
oper1b = regal: oper2b = getmem8(regcs, ip): StepIP 1
flag_log8(oper1b And oper2b)
If debugmode = 1 Then dprint " TEST 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
Case &HA9 'A9 TEST eAX Iv
oper1 = ((regah Shl 8) Or regal): oper2 = getmem16(regcs, ip): StepIP 2
flag_log16(oper1 And oper2)
Case &HAA 'AA STOSB
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
putmem8 reges, regdi, regal
If df Then regdi = regdi - 1 Else regdi = regdi + 1
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HAB 'AB STOSW
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
putmem16 reges, regdi, ((regah Shl 8) Or regal)
If df Then regdi = regdi - 2 Else regdi = regdi + 2
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HAC 'AC LODSB
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
regal = getmem8(useseg, regsi)
If df Then regsi = regsi - 1 Else regsi = regsi + 1
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HAD 'AD LODSW
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
oper1 = getmem16(useseg, regsi)
regah = oper1 Shr 8: regal = oper1 And 255
If df Then regsi = regsi - 2 Else regsi = regsi + 2
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
Loop Until reptype = 0
Case &HAE 'AE SCASB
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
oper1b = getmem8(reges, regdi): oper2b = regal
flag_sub8 oper1b, oper2b
If debugmode = 1 Then dprint " CMP 8-bit: oper1 = " + Hex$(oper1b) + "h, oper2 = " + Hex$(oper2b) + "h"
If df Then regdi = regdi - 1 Else regdi = regdi + 1
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
If (reptype = 1) And (zf = 0) Then Exit Do
If (reptype = 2) And (zf = 1) Then Exit Do
Loop Until reptype = 0
Case &HAF 'AF SCASW
Do
If (reptype <> 0) And (((regch Shl 8) Or regcl) = 0) Then Exit Do
oper1 = getmem16(reges, regdi): oper2 = ((regah Shl 8) Or regal)
flag_sub16 oper1, oper2
If debugmode = 1 Then dprint " CMP 16-bit: oper1 = " + Hex$(oper1) + "h, oper2 = " + Hex$(oper2) + "h"
If df Then regdi = regdi - 2 Else regdi = regdi + 2
If (reptype <> 0) Then
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
End If
If (reptype = 1) And (zf = 0) Then Exit Do
If (reptype = 2) And (zf = 1) Then Exit Do
Loop Until reptype = 0
Case &HB0 'B0 MOV regal Ib
regal = getmem8(regcs, ip): StepIP 1
Case &HB1 'B1 MOV regcl Ib
regcl = getmem8(regcs, ip): StepIP 1
Case &HB2 'B2 MOV regdl Ib
regdl = getmem8(regcs, ip): StepIP 1
Case &HB3 'B3 MOV regbl Ib
regbl = getmem8(regcs, ip): StepIP 1
Case &HB4 'B4 MOV regah Ib
regah = getmem8(regcs, ip): StepIP 1
Case &HB5 'B5 MOV regch Ib
regch = getmem8(regcs, ip): StepIP 1
Case &HB6 'B6 MOV regdh Ib
regdh = getmem8(regcs, ip): StepIP 1
Case &HB7 'B7 MOV regbh Ib
regbh = getmem8(regcs, ip): StepIP 1
Case &HB8 'B8 MOV eAX Iv
oper1 = getmem16(regcs, ip): StepIP 2
regah = oper1 Shr 8: regal = oper1 And 255
Case &HB9 'B9 MOV eCX Iv
oper1 = getmem16(regcs, ip): StepIP 2
regch = oper1 Shr 8: regcl = oper1 And 255
Case &HBA 'BA MOV eDX Iv
oper1 = getmem16(regcs, ip): StepIP 2
regdh = oper1 Shr 8: regdl = oper1 And 255
Case &HBB 'BB MOV eBX Iv
oper1 = getmem16(regcs, ip): StepIP 2
regbh = oper1 Shr 8: regbl = oper1 And 255
Case &HBC 'BC MOV eSP Iv
regsp = getmem16(regcs, ip): StepIP 2
Case &HBD 'BD MOV eBP Iv
regbp = getmem16(regcs, ip): StepIP 2
Case &HBE 'BE MOV eSI Iv
regsi = getmem16(regcs, ip): StepIP 2
Case &HBF 'BF MOV eDI Iv
regdi = getmem16(regcs, ip): StepIP 2
Case &HC0 'C0 GRP2 byte imm8 (80186+)
modregrm()
oper1b = readrm8(rm)
oper2b = getmem8(regcs, ip): StepIP 1
writerm8(rm, op_grp2_8(oper2b))
Case &HC1 'C1 GRP2 word imm8 (80186+)
modregrm()
oper1 = readrm16(rm)
oper2 = getmem8(regcs, ip): StepIP 1
writerm16(rm, op_grp2_16(oper2))
Case &HC2 'C2 RET Iw
oper1 = getmem16(regcs, ip)
ip = pop
regsp = regsp + oper1
Case &HC3 'C3 RET
ip = pop
Case &HC4 'C4 LES Gv Mp
modregrm()
getea(rm)
putreg16(reg, read86(ea) + read86(ea + 1) * 256)
reges = read86(ea + 2) + read86(ea + 3) * 256
Case &HC5 'C5 LDS Gv Mp
modregrm()
getea(rm)
putreg16(reg, read86(ea) + read86(ea + 1) * 256)
regds = read86(ea + 2) + read86(ea + 3) * 256
Case &HC6 'C6 MOV Eb Ib
modregrm()
writerm8(rm, getmem8(regcs, ip)): StepIP 1
Case &HC7 'C7 MOV Ev Iv
modregrm()
writerm16(rm, getmem16(regcs, ip)): StepIP 2
Case &hC8 'C8 ENTER (80186+)
stacksize = getmem16(regcs, ip): StepIP 2
nestlev = getmem8(regcs, ip): StepIP 1
push regbp
frametemp = regsp
If nestlev <> 0 Then
For temp16 = 1 To nestlev - 1
regbp = regbp - 2
push regbp
Next temp16
push regsp
End If
regbp = frametemp
regsp = regbp - stacksize
Case &HC9 'C9 LEAVE (80186+)
regsp = regbp
regbp = pop
Case &HCA 'CA RETF Iw
oper1 = getmem16(regcs, ip)
ip = pop: regcs = pop
regsp = regsp + oper1
Case &HCB 'CB RETF
ip = pop: regcs = pop
Case &HCC 'CC INT 3
intcall86 3
Case &HCD 'CD INT Ib
oper1 = getmem8(regcs, ip): StepIP 1
intcall86 oper1
Case &HCE 'CE INTO
If of Then intcall86 4
Case &HCF 'CF IRET
ip = pop: regcs = pop
decodeflagsword pop
Case &HD0 'D0 GRP2 Eb 1
modregrm()
oper1b = readrm8(rm)
writerm8(rm, op_grp2_8(1))
Case &HD1 'D1 GRP2 Ev 1
modregrm()
oper1 = readrm16(rm)
writerm16(rm, op_grp2_16(1))
Case &HD2 'D2 GRP2 Eb regcl
modregrm()
oper1b = readrm8(rm)
writerm8(rm, op_grp2_8(regcl))
Case &HD3 'D3 GRP2 Ev regcl
modregrm()
oper1 = readrm16(rm)
writerm16(rm, op_grp2_16(regcl))
Case &HD4 'D4 AAM I0
oper1 = getmem8(regcs, ip): StepIP 1
If oper1 = 0 Then intcall86 0: Exit Sub 'division by zero
regah = (regal \ oper1) And 255
regal = (regal Mod oper1) And 255
flag_szp16 ((regah Shl 8) Or regal)
Case &HD5 'D5 AAD I0
oper1 = getmem8(regcs, ip): StepIP 1
regal = (regah * oper1 + regal) And 255
regah = 0
flag_szp16(regah * oper1 + regal)
sf = 0
Case &HD7 'D7 XLAT
regal = read86(useseg * 16 + ((regbh Shl 8) Or regbl) + regal)
Case &hD8 To &hDF 'escape
StepIP 1
Case &HE0 'E0 LOOPNZ Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
If (((regch Shl 8) Or regcl) <> 0) And (zf = 0) Then ip = ip + temp16
Case &HE1 'E1 LOOPZ Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
If (((regch Shl 8) Or regcl) <> 0) And (zf = 1) Then ip = ip + temp16
Case &HE2 'E2 LOOP Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
putreg16(regcx, ((regch Shl 8) Or regcl) - 1)
If ((regch Shl 8) Or regcl) <> 0 Then ip = ip + temp16
Case &HE3 'E3 JCXZ Jb
temp16 = signext(getmem8(regcs, ip)): StepIP 1
If ((regch Shl 8) Or regcl) = 0 Then ip = ip + temp16
Case &HE4 'E4 IN regal Ib
oper1b = getmem8(regcs, ip)
StepIP 1
regal = portin(oper1b)
Case &HE5 'E5 IN eAX Ib
oper1b = getmem8(regcs, ip)
StepIP 1
putreg16(regax, portin(oper1b))
Case &HE6 'E6 OUT Ib regal
oper1b = getmem8(regcs, ip)
StepIP 1
portout16 = 0
portout oper1b, regal
Case &HE7 'E7 OUT Ib eAX
oper1b = getmem8(regcs, ip)
StepIP 1
portout16 = 1
portout oper1b, ((regah Shl 8) Or regal)
Case &HE8 'E8 CALL Jv
oper1 = getmem16(regcs, ip): StepIP 2
push ip
ip = ip + oper1
Case &HE9 'E9 JMP Jv
oper1 = getmem16(regcs, ip): StepIP 2
ip = ip + oper1
Case &HEA 'EA JMP Ap
oper1 = getmem16(regcs, ip): StepIP 2
oper2 = getmem16(regcs, ip)
ip = oper1: regcs = oper2
Case &HEB 'EB JMP Jb
oper1 = signext(getmem8(regcs, ip)): StepIP 1
ip = ip + oper1
Case &HEC 'EC IN regal regdx
oper1 = ((regdh Shl 8) Or regdl)
regal = portin(oper1)
Case &HED 'ED IN eAX regdx
oper1 = ((regdh Shl 8) Or regdl)
putreg16(regax, portin(oper1))
Case &HEE 'EE OUT regdx regal
oper1 = ((regdh Shl 8) Or regdl)
portout16 = 0
portout oper1, regal
Case &HEF 'EF OUT regdx eAX
oper1 = ((regdh Shl 8) Or regdl)
portout16 = 1
portout oper1, ((regah Shl 8) Or regal)
Case &HF0 'F0 LOCK
Case &HF4 'F4 HLT
ip = ip - 1
If running <> 2 Then
cprint "HLT executed."
SDL_WM_SetCaption("Fake86 [halted]", 0)
running = 2
End If
Case &HF5 'F5 CMC
If cf = 0 Then cf = 1 Else cf = 0
Case &HF6 'F6 GRP3a Eb
modregrm()
oper1b = readrm8(rm)
op_grp3(0)
If (reg > 1) And (reg < 4) Then
writerm8(rm, res8)
End If
Case &HF7 'F7 GRP3b Ev
modregrm()
oper1 = readrm16(rm)
op_grp3(1)
If (reg > 1) And (reg < 4) Then
writerm16(rm, res16)
End If
Case &HF8 'F8 CLC
cf = 0
Case &HF9 'F9 STC
cf = 1
Case &HFA 'FA CLI
ifl = 0
Case &HFB 'FB STI
ifl = 1
Case &HFC 'FC CLD
df = 0
Case &HFD 'FD STD
df = 1
Case &HFE 'FE GRP4 Eb
modregrm()
oper1b = readrm8(rm): oper2b = 1
If reg = 0 Then
temp = cf
res8 = oper1b + oper2b
flag_add8 oper1b, oper2b
cf = temp: writerm8(rm, res8)
ElseIf reg = 1 Then
temp = cf
res8 = oper1b - oper2b
flag_sub8 oper1b, oper2b
cf = temp: writerm8(rm, res8)
Else
intcall86 6
End If
Case &HFF 'FF GRP5 Ev
modregrm()
oper1 = readrm16(rm)
op_grp5()
Case Else
intcall86 6
End Select
EDIT: gotta split this into 2 posts, it's too big to fit in 1...